1. Technical Field
The disclosure relates to a semiconductor device.
2. Description of Related Art
As illustrated in FIG. 10 by way of example, a field effect transistor (FET) including an n-type drift region 6, p-type well regions 12, n-type source regions 14, insulating film 16, and a gate electrode 18 is known. The p-type well regions 12 are surrounded by the n-type drift region 6, and are exposed to a surface of a semiconductor substrate. The n-type source regions 14 are surrounded by the p-type well regions 12, and are exposed to the surface of the semiconductor substrate. The gate electrode 18 is opposed, via the insulating film 16, to a surface of each p-type well region 12 in a range in which the n-type drift region 6 and the n-type source region 14 are separated or spaced from each other.
While no positive voltage is applied to the gate electrode 18, the n-type drift region 6 and the n-type source region 14 are separated by the p-type well region 12, and high resistance appears between the drift region 6 and each source region 14. If a positive voltage is applied to the gate electrode 18, an inversion layer is formed in a surface of the p-type well region 12 in a range opposed to the gate electrode 18 via the insulating film 16, namely, a surface of the p-type well region 12 in a range in which the n-type drift region 6 and the n-type source region 14 are separated or spaced from each other, and low resistance appears between the drift region 6 and the source region 14. With the structure of FIG. 10, the FET is obtained. In FIG. 10, reference number 4 denotes drain region, and reference number 2 denotes drain electrode.
In the FET, the resistance (on-resistance) between the source region 14 and the drain region 4 is required to be low in a condition where a positive voltage is applied to the gate electrode 18. Also, in a condition where no positive voltage is applied to the gate electrode 18, the drain region 4 has a high potential, and the source region 14 and the gate electrode 18 have low potentials. In the FET, even if the potential of the drain region 4 becomes high, it is required to prevent electric current from flowing into the source region 14 or the gate electrode 18 (these components 14, 18 have high withstand voltages).
In order to reduce the on-resistance, it is advantageous to increase the impurity concentration of the n-type drift region 6. However, if the impurity concentration of the n-type drift region 6 is increased, a potential difference between a surface and a rear surface of the insulating film 16 becomes large when no positive voltage is applied to the gate electrode 18, and current is more likely to flow into the gate electrode 18. If the impurity concentration of the n-type drift region 6 is increased, the gate withstand voltage is reduced. Also, if the impurity concentration of the n-type drift region 6 is increased, the intensity of electric field in the vicinity of an interface between the p-type well region 12 and the n-type drift region 6 is increased, in a condition where no positive voltage is applied to the gate electrode 18, which may result in occurrence of an avalanche breakdown, and electric current is more likely to flow into the n-type source region 14. If the impurity concentration of the n-type drift region 6 is increased, the withstand voltage between the drain and the source is reduced. Namely, in the FET, there is a trade-off relationship that, if the on-resistance is reduced, the gate withstand voltage is reduced, and the withstand voltage between the drain and the source is reduced.
An attempt to solve the trade-off problem is disclosed in Japanese Patent Application Publication No. 2012-064741 (JP 2012-064741 A). According to a technology disclosed in this publication, the impurity concentration of an n-type region located between a pair of p-type well regions is controlled so as to vary from portion to portion, as shown in FIG. 11. Namely, a pair of n-type impurity high-concentration regions 24 are provided in portions of the n-type region which contact with side faces of the p-type well regions 12, and an n-type impurity low-concentration region 22 is provided in a portion of the n-type region which is located between the high-concentration regions 24.